Design Verification Engineer applicants have rated the interview process at Meta with 3.1 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 43% positive. To compare, the company-average is 56.5% positive. This is according to Glassdoor user ratings.
Candidates applying for Design Verification Engineer roles take an average of 22 days to get hired, when considering 7 user submitted interviews for this role. To compare, the hiring process at Meta overall takes an average of 31 days.
Common stages of the interview process at Meta as a Design Verification Engineer according to 7 Glassdoor interviews include:
Phone interview: 36%
Skills test: 18%
Other: 9%
Group panel interview: 9%
Personality test: 9%
One on one interview: 9%
IQ intelligence test: 9%
Here are the most commonly searched roles for interview reports -
Average. Focus on basics of sv and uvm. Understanding of uvm config db and other benefits of uvm is needed. Sv constraints is v important. All the comp of tb specifically scoreboard is vital
Phone screens followed by interview round with presentations. Questions testing mechanical engineering fundamentals and some test-specific questions, such as statistics or mechanical design for repeatability. Presentation is about a project you worked on previously.
HR guidance to the process was on top. There was a long delay of 3 weeks+ to schedule forst round itself
first Followed by 2 edcoding tech rounds initially.
Following which there would be loop interviews. Followed by HR round at the end.
Interview questions [1]
Question 1
Sv constraints on memory block and region. GLS questions on debug flow.